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figure 1. application with vin to ground short protection, using p-mosfet sensing a8521-ds features and benefits ? aec-q100 qualified ? wide input voltage range of 5 to 40 v for start/stop, cold crank and load dump requirements ? fully integrated led current sinks and boost converter with 60 v dmos ? sync function to synchronize boost converter switching frequency up to 2.3 mhz, allowing operation above the am band ? excellent input voltage transient response ? single resistor primary ovp minimizes v out leakage ? internal secondary ovp for redundant protection ? led current of 80 ma per channel ? drives up to 12 series leds in 4 parallel strings ? 0.7% to 0.8% led to led matching accuracy ? pwm and analog dimming inputs ? 5000:1 pwm dimming at 200 hz ? provides driver for external pmos input disconnect switch ? extensive protection against: ? shorted boost switch or inductor ? shorted fset or iset resistor ? shorted output ? open or shorted led pin ? open boost schottky ? overtemperature (otp) wide input voltage range, high efficiency fault tolerant led driver package: 20-pin tssop with exposed thermal pad (suffix lp) typical application circuit not to scale a8521 continued on the next page? gate sw q1 d1 l1 c vdd ovp v out r ovp c out r sc r adj vsense vin vdd pwm/en apwm iset fset/sync agnd pgnd comp c p r z c z led4 led1 led2 led3 fault pad a8521 150 v c 10 h 2 a / 60 v 137 k 0.033 249 100 k r iset 8.25 k r fset 10 k 4.7 f 50 v c in 4.7 f 50 v c c 22 nf r c 20 0.1 f 0.47 f 120 pf v in 8 to 16 v description the a8521 is a multi-output white led driver for small-size lcd backlighting. it integrates a current-mode boost converter with internal power switch and four current sinks. the boost converter can drive up to 48 leds, 12 leds per string, at 80 ma. the led sinks can be paralleled together to achieve even higher led currents, up to 320 ma. the a8521 can operate with a single power supply, from 5 to 40 v, which allows the part to withstand load dump conditions encountered in automotive systems. the a8521 can drive an external p-fet to disconnect the input supply from the system in the event of a fault. the a8521 provides protection against output short and overvoltage, open or shorted diode, open or shorted led pin, shorted boost switch or inductor, shorted fset or iset resistor, and ic overtemperature. a dual level cycle-by-cycle current limit function provides soft start and protects the internal current switch against high current overloads. the a8521 has a synchronization pin that allows pwm switching frequencies to be synchronized in the range of 580 khz to 2.3 mhz. the high switching frequency allows the a8521 to operate above the am radio band. applications: lcd backlighting or led lighting for: ? automotive infotainment ? automotive cluster ? automotive center stack
wide input voltage range, high efficiency fault tolerant led driver a8521 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings* characteristic symbol notes rating unit ledx pins ?0.3 to 55 v ovp pin ?0.3 to 60 v vin, vsense, gate pins vsense and gate pins should not exceed v in by more than 0.4 v ?0.3 to 40 v sw pin continuous ?0.6 to 62 v t < 50 ns ?1.0 v f a u l t pin -0.3 to 40 v iset, fset, apwm, comp pins ?0.3 to 5.5 v all other pins ?0.3 to 7 v operating ambient temperature t a range k ?40 to 125 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc *stresses beyond those listed in this table may cause permanent damage to the device. the absolute maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the elec trical characteristics table is not implied. exposure to absolute maximum-rated conditions for extended periods may affect device reli ability. selection guide part number packing* A8521KLPTR-T 4000 pieces per 13-in. reel *contact allegro ? for additional packing options table of contents specifications 2 pin-out diagram and terminal list 3 characteristic performance 8 functional description 11 enabling the ic 11 powering up: led pin short-to-ground check 11 soft start function 13 frequency selection 13 sync 14 led current setting and led dimming 15 pwm dimming 15 apwm pin 16 analog dimming 18 description (continued) the a8521 is provided in a 20-pin tssop package (suffix lp) with an exposed pad for enhanced thermal dissipation. it is lead (pb) free, with 100% matte tin lead frame plating. overvoltage protection 19 boost switch overcurrent protection 21 input overcurrent protection and disconnect switch 22 setting the current sense resistor 23 input uvlo 23 vdd 23 shutdown 23 fault protection during operation 24 application information 26 design example for boost configuration 26 design example for sepic configuration 30 package outline drawing 34
wide input voltage range, high efficiency fault tolerant led driver a8521 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pin-out diagram terminal list table number name function 1 gate output gate driver pin for external p-channel fet control. 2 vsense connect this pin to the negative sense side of the current sense resistor r sc . the threshold voltage is measured as v in ? v sense . there is also a fixed current sink to allow for trip threshold adjustment. 3 vin input power to the a8521 as well as the positive input used for current sense resistor. 4 f a u l t indicates a fault condition. connect a 100 k resistor between this pin and the required logic level voltage. the pin is an open drain type configuration that will be pulled low when a fault occurs. 5 comp output of the error amplifier and compensation node. connect a series r z -c z network from this pin to ground for control loop compensation. 6 apwm analog trimming option for dimming. applying a digital pwm signal to this pin adjusts the internal i set current. 7 pwm/en pwm dimming pin, used to control the led intensity by using pulse width modulation. also used to enable the a8521. 8 fset/sync frequency/synchronization pin. a resistor r fset from this pin to ground sets the switching frequency. this pin can also be used to synchronize two or more a8521s in the system. the maximum synchronization frequency is 2.3 mhz. 9 iset connect the r iset resistor between this pin and ground to set the 100% led current. 10 agnd led signal ground. 11,12,13,14 ledx connect the cathodes of the led strings to these pins. 15 vdd output of internal ldo; connect a 0.1 f decoupling capacitor between this pin and ground. 16,17.18 pgnd power ground for internal dmos device. 19 ovp overvoltage condition (ovp) sense; connect the r ovp resistor from v out to this pin to adjust the overvoltage protection. 20 sw the drain of the internal dmos switch of the boost converter. ?pad exposed pad of the package providing enhanced thermal dissipation. this pad must be connected to the ground plane(s) of the pcb with at least 8 vias, directly in the pad. thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value unit package thermal resistance r ja on 2-layer pcb, 3 in. 2 40.0 oc/w on 4-layer pcb based on jedec standard (estimated) 29.0 oc/w *additional thermal information available on the allegro website 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 gate vsense vin fault comp apwm pwm/en fset/sync iset agnd sw ovp pgnd pgnd pgnd vdd led1 led2 led3 led4
wide input voltage range, high efficiency fault tolerant led driver a8521 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional block diagram vdd regulator uvlo internal soft start enable pwm thermal shutdown open/short led detect iset fault led driver 1.235 v ref driver circuit internal v cc internal v cc v ref internal v cc v ref v ref i ss i ss i adj goff 100 k agnd current sense input current sense amplifier pmos driver diode open sense ovp sense oscillator sw vin fset/sync comp vsense gate pwm/en apwm pad pgnd agnd iset ovp led4 led1 led2 led3 fault agnd pgnd + ? + ? + ? + ? + ? fault fault fault
wide input voltage range, high efficiency fault tolerant led driver a8521 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics 1,2 valid at v in = 16 v, t a = 25c, indicates specifications guaranteed by design and characterization over the full operating temperature range with t a = t j = ?40c to 125c; unless otherwise noted characteristics symbol test conditions min. typ. max. unit input voltage specifications operating input voltage range 3 v in 5 ? 40 v uvlo start threshold v uvlorise v in rising ? ? 4.35 v uvlo stop threshold v uvlofall v in falling ? ? 3.90 v uvlo hysteresis 2 v uvlohys 300 450 600 mv input currents input quiescent current i q pwm/en = v ih ; sw = 2 mhz, no load ? 5.5 10 ma input sleep supply current i qsleep v in = 16 v, v pwmen = v fsetsync = 0 v ? 2 10.0 a input logic levels (pwm/en and apwm) input logic level-low v il v in throughout operating input voltage range ? ? 400 mv input logic level-high v ih v in throughout operating input voltage range 1.5 ? ? v pwm/en pin open drain pull-down resistor r pwmen pwm/en = 5 v 60 100 140 k apwm pull-down resistor r apwm pwm/en = v ih 60 100 140 k apwm apwm frequency 2 f apwm v ih = 2 v, v il = 0 v 20 ? 1000 khz error amplifier open loop voltage gain a vol 44 48 52 db transconductance g m i comp = 10 a 750 990 1220 a/v source current i ea(src) v comp = 1.5 v ? ?350 ? a sink current i ea(sink) v comp = 1.5 v ? 350 ? a comp pin pull-down resistance r comp f a u l t = 0 ? 2000 ? overvoltage protection overvoltage threshold v ovp(th) ovp connected to v out 7.7 8.1 8.5 v ovp sense current i ovph 188 199 210 a ovp leakage current i ovplkg r ovp = 40.2 k , v in = 16 v, pwm/en = v il ? 0.1 1 a secondary overvoltage protection v ovp(sec) 53 55 58 v boost switch switch on-resistance r sw i sw = 0.750 a, v in = 16 v 75 300 600 m switch leakage current i swlkg v sw = 16 v, pwm/en = v il ? 0.1 1 a switch current limit i sw(lim) 3.0 3.5 4.2 a secondary switch current limit 2 i sw(lim2) higher than i sw(lim) (max) for all conditions, device latches when detected ? 7.00 ? a soft start boost current limit i swss(lim) initial soft start current for boost switch ? 700 ? ma minimum switch on-time t swontime 60 85 111 ns minimum switch off-time t swofftime 30 47 68 ns continued on the next page?
wide input voltage range, high efficiency fault tolerant led driver a8521 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com oscillator frequency oscillator frequency f sw r fset = 10 k 1.8 2 2.2 mhz r fset = 20 k 0.9 1 1.1 mhz r fset = 35.6 k 520 580 640 khz fset/sync pin voltage v fset r fset = 10 k ? 1.00 ? v fset frequency range f fset 580 ? 2500 khz synchronization synchronized pwm frequency f swsync 580 ? 2300 khz synchronization input minimum off-time t pwsyncoff 150 ?? ns synchronization input minimum on-time t pwsyncon 150 ?? ns sync input logic voltage v sync(h) fset/sync pin, high level ?? 0.4 v v sync(l) fset/sync pin, low level 2.0 ?? v led current sinks ledx accuracy err led i set = 120 a ?? 3% ledx matching ledx i set = 120 a ?? 3% ledx regulation voltage v led v led1 =v led2 =v led3 =v led4 , i set = 120 a 600 700 800 mv i set to i ledx current gain a iset i set = 120 a 633 653 672 a/a iset pin voltage v iset 0.988 1.003 1.018 v allowable iset current i set 20 ? 120 a soft start ledx current i ledss current through each enabled ledx pin during soft start ? 2.0 ? ma maximum pwm dimming until off-time 2 t pwml measured while pwm/en = low, during dimming control and internal references are powered-on (exceeding t pwml results in shutdown) ? 32,750 ? f sw cycles minimum pwm on-time t pwmh first cycle when powering-up device ? 0.75 2 s pwm high to led-on delay t dpwm(on) time between pwm enable and led current reaching 90% of maximum ? 0.5 1 s pwm low to led-off delay t dpwm(off) time between pwm enable going low and led current reaching 10% of maximum ? 360 500 ns electrical characteristics 1,2 (continued) valid at v in = 16 v, t a = 25c, indicates specifications guaranteed by design and characterization over the full operating temperature range with t a = t j = ?40c to 125c; unless otherwise noted characteristics symbol test conditions min. typ. max. unit continued on the next page?
wide input voltage range, high efficiency fault tolerant led driver a8521 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics 1,2 (continued) valid at v in = 16 v, t a = 25c, indicates specifications guaranteed by design and characterization over the full operating temperature range with t a = t j = ?40c to 125c; unless otherwise noted characteristics symbol test conditions min. typ. max. unit gate pin gate pin sink current i gsink v gs = v in ?? 104 ? a gate fault shutdown greater than 2x current 2 t gfault2 ?? 3 s gate fault shutdown greater than 1?2x current t gfault1 ? 10,000 ? f sw cycles gate voltage v gs gate to source voltage measured when gate is on ? ?6.7 ? v vsense pin vsense pin sink current i adj 18.8 20.3 21.8 a vsense trip point v sensetrip1 measured between vin and vsense, r adj = 0 94 104 114 mv vsense 2x trip 2 v sensetrip2 2x v sensetrip , instantaneous shutdown, r adj = 0 ? 180 ? mv f a u l t pin f a u l t pull-down voltage v fault i fault = 1 ma ?? 0.5 v f a u l t pin leakage current i faultlkg v fault = 5 v ?? 1 a thermal protection (tsd) thermal shutdown threshold 2 t sd temperature rising ? 165 ? oc thermal shutdown hysteresis 2 t sdhys ? 20 ? oc 1 for input and output current specifications, negative current is defined as coming out of the node or pin (sourcing); positive current is defined as going into the node or pin (sinking). 2 ensured by design and characterization, not production tested. 3 minimum v in = 5 v is only required at startup. after startup is completed, the ic is able to function down to v in = 4 v.
wide input voltage range, high efficiency fault tolerant led driver a8521 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 7.7 7.6 7.8 7.9 8.0 8.1 8.2 8.3 8.4 v ovp(th) (v) 190 192 194 196 198 200 202 204 206 208 210 i ovph ( a) 3.60 3.61 3.62 3.63 3.64 3.65 3.66 3.67 3.68 3.69 3.70 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 f sw (mhz) switching frequency ovp pin sense current ovp pin overvoltage threshold 4.00 4.05 4.10 4.15 4.20 4.25 4.30 4.35 4.40 v uvlorise (v) v uvlofall (v) 0 1 2 3 4 5 6 7 8 9 10 i qsleep ( a) vin input sleep mode current versus ambient temperature vin uvlo start threshold voltage vin uvlo stop threshold voltage versus ambient temperature versus ambient temperature versus ambient temperature versus ambient temperature versus ambient temperature temperature (c) temperature (c) temperature (c) temperature (c) temperature (c) temperature (c) -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 130 0 -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 130 0 -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 130 0 -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 130 0 -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 130 0 -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 130 0 characteristic performance t a = t j
wide input voltage range, high efficiency fault tolerant led driver a8521 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 20.0 20.1 20.2 20.3 20.4 20.5 20.6 20.7 20.8 i adj ( a) vsense pin sink current -6.9 -6.8 -6.7 -6.6 -6.5 -6.4 -6.3 v gs (v) input disconnect switch voltage gate to source temperature (c) temperature (c) versus ambient temperature versus ambient temperature -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 130 0 -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 130 0 -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 130 0 -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 130 0 -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 130 0 3 2 1 0 -1 -2 -3 ledx (%) led to led matching accuracy 670 665 660 655 650 645 640 a iset (a/a) i set to led current gain versus ambient temperature 83 82 81 80 79 78 77 76 75 i led (ma) temperature (c) temperature (c) i set = 120 a temperature (c) led current versus ambient temperature versus ambient temperature
wide input voltage range, high efficiency fault tolerant led driver a8521 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 100 95 90 85 80 75 e ? ciency (%) 96 94 92 90 88 86 84 82 80 78 e ? ciency (%) input voltage, v in (v) e ? ciency for various led con gura ons i led = 70 ma, led v f 3.2 v e ? ciency for various led con gura ons i led = 80 ma, led v f 3.2 v input voltage, v in (v) 4 strings, 6 series leds each 4 strings, 7 series leds each 4 strings, 8 series leds each 4 strings, 6 series leds each 4 strings, 7 series leds each 4 strings, 8 series leds each 5 7 9 11131517 5 7 9 11 13 15 17
wide input voltage range, high efficiency fault tolerant led driver a8521 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the a8521 incorporates a current-mode boost controller with internal dmos switch, and four led current sinks. it can be used to drive four led strings of up to 12 white leds in series, with current up to 80 ma per string. for optimal efficiency, the output of the boost stage is adaptively adjusted to the mini- mum voltage required to power all of the led strings. this is expressed by the following equation: v out = max ( v led1 ,..., v led4 ) + v reg (1) where v ledx is the voltage drop across led strings 1 through 4, and v reg is the regulation voltage of the led current sinks (typi- cally 0.7 v at the maximum led current). enabling the ic the ic turns on when a logic high signal is applied on the pwm/en pin with a minimum duration of t pwmh for the first clock cycle, and the input voltage present on the vin pin is greater than the 4.35 v necessary to clear the uvlo (v uvlorise ) threshold. the power-up sequence is shown in figure 2. before the leds are enabled, the a8521 driver goes through a system check to determine if there are any possible fault conditions that might prevent the system from functioning correctly. also, if the fset/sync pin is pulled low, the ic will not power-up. more information on the fset/sync pin can be found in the sync section of this datasheet. powering up: led pin short-to-ground check the vin pin has a uvlo function that prevents the a8521 from powering-up until the uvlo threshold is reached. after the vin pin goes above uvlo, and a high signal is present on the pwm/en pin, the ic proceeds to power-up. as shown in figure 3, at this point the a8521 enables the disconnect switch and checks if any ledx pins are shorted to ground and/or are not used. the led detect phase starts when the gate voltage of the disconnect switch is equal to v in ? 4.5 v. after the voltage threshold on the ledx pins exceeds 120 mv, a delay of between 3000 and 4000 clock cycles is used to determine the status of the pins. thus, the led detection duration varies with the switching frequency, as shown in the following table: switching frequency (mhz) detection time (ms) 2 1.5 to 2 1 3 to 4 0.800 3.75 to 5 0.600 5 to 6.7 the led pin detection voltage thresholds are as follows: led pin voltage led pin status action <70 mv short-to-ground power-up is halted 150 mv not used led removed from operation 325 mv led pin in use none functional description figure 2. power-up diagram; shows vdd (ch1, 2 v/div.), fset/sync (ch2, 1 v/div.), iset (ch3, 1 v/div.), and pwm/en (ch4, 2 v/div.) pins, time = 200 s/div. t vdd pwm/en fset/sync iset c1 c3 c4 c2 figure 3. power-up diagram; shows the relationship of an ledx pin with respect to the gate voltage of the disconnect switch (if used) during the led detect phase, as well as the duration of the led detect phase for a switching frequency of 2 mhz; shows gate (ch1, 5 v/div.), led (ch2, 500 mv/div.), iset (ch3, 1 v/div.), and pwm/en (ch4, 5 v/div.) pins, time = 500 s/div. t gate gate = v in ? 4.5 v led detection period pwm/en ledx iset c1 c3 c4 c2
wide input voltage range, high efficiency fault tolerant led driver a8521 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 4a. an led detect occurring when both led pins are selected to be used; shows led1 (ch1, 500 mv/div.), led2 (ch2, 500 mv/div.), iset (ch3, 1 v/div.), and pwm/en (ch4, 5 v/div.) pins, time = 500 s/div. 4b. example with led2 pin not being used; the detect voltage is about 150 mv; shows led1 (ch1, 500 mv/div.), led2 (ch2, 500 mv/div.), iset (ch3, 1 v/div.), and pwm/en (ch4, 5 v/div.) pins, time = 500 s/div. 4c. example with one led shorted to ground. the ic will not proceed with power-up until the shorted led pin is released, at which point the led is checked to see if it is being used; shows led1 (ch1, 500 mv/div.), led2 (ch2, 500 mv/div.), iset (ch3, 1 v/div.), and pwm/en (ch4, 5 v/div.) pins, time = 1 ms/div. t led detection period pwm/en led2 led1 iset c1 c3 c4 c2 t pin shorted short removed pwm/en led2 led1 iset c1 c3 c4 c2 t led detection period pwm/en led2 led1 iset c1 c3 c4 c2
wide input voltage range, high efficiency fault tolerant led driver a8521 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com all unused pins should be connected with a 2.37 k resistor to ground, as shown in figure 5. the unused pin, with the pull-down resistor, will be taken out of regulation at this point and will not contribute to the boost regulation loop. if a ledx pin is shorted to ground the a8521 will not proceed with soft start until the short is removed from the ledx pin. this prevents the a8521 from powering-up and putting an uncon- trolled amount of current through the leds. soft start function during soft start the ledx pins are set to sink (i ledss ) and the boost switch current is reduced to the i swss(lim) level to limit the inrush current generated by charging the output capacitors. when the converter senses that there is enough voltage on the ledx pins the converter proceeds to increase the led current to the preset regulation current and the boost switch current limit is switched to the i sw(lim) level to allow the a8521 to deliver the necessary output power to the leds. this is shown in figure 6. frequency selection the switching frequency on the boost regulator is set by the resis- tor connected to the fset/sync pin. the switching frequency can be can be anywhere from 580 khz to 2.3 mhz. figure 7 shows the typical switching frequencies, in mhz, for given resis- tor values, in k . in case during operation a fault occurs that will increase the switching frequency, the fset/sync pin is clamped to a maximum switching frequency of no more than 3.5 mhz. if the fset/sync pin is shorted to gnd the part will shut down. for more details see the fault mode table later in this datasheet. figure 5. channel select setup: (left) using only led1, led2, and led3, and (right) using all four channels. 2.37 k led1 led2 led3 led4 gnd a8521 led1 led2 led3 led4 gnd a8521 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 f sw (mhz) resistance for r set (k ) 10.0 30.0 20.0 12.5 32.5 22.5 17.5 15.0 25.0 35.0 figure 6. startup diagram showing the input current, output voltage, and output current; shows i out (ch1, 200 ma/div.), i in (ch2, 1 a/div.), v out (ch3, 20 v/div.), and pwm/en (ch4, 5 v/div.), time = 1 ms/div. figure 7. typical switching frequency versus value of r fset resistor. t inrush current caused by enabling the disconnect switch (when used) operation during i swss(lim) normal operation i sw(lim) pwm/en i in i out v out c1 c3 c4 c2
wide input voltage range, high efficiency fault tolerant led driver a8521 14 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com sync the a8521 can also be synchronized using an external clock on the fset/sync pin. figure 8 shows the correspondence of a sync signal and the fset/sync pin, and figure 9 shows the result when a sync signal is detected: the led current does not show any variation while the frequency changeover occurs. at power-up if the fset/sync pin is held low, the ic will not power-up. only when the fset/sync pin is tri-stated to allow the pin to rise, to about 1 v, or when a synchronization clock is detected, will the a8521 try to power-up. the basic requirement of the sync signal is 150 ns minimum on- time and 150 ns minimum off time, as indicated by the specifica- tions for t pwsyncon and t pwsyncoff . figure 10 shows the timing for a synchronization clock into the a8521 at 2.2 mhz. thus any pulse with a duty cycle of 33% to 66% at 2.2 mhz can be used to synchronize the ic. the sync pulse duty cycle ranges for selected switching fre- quencies are: sync pulse frequency (mhz) duty cycle range (%) 2.2 33 to 66 2 30 to 70 1 15 to 85 0.800 12 to 88 0.600 9 to 91 if during operation a sync clock is lost, the ic will revert to the preset switching frequency that is set by the resistor r fset . dur- ing this period the ic will stop switching for a maximum period of about 7 s to allow the sync detection circuitry to switch over to the externally preset switching frequency. if the clock is held low for more than 7 s, the a8521 will shut down. in this shutdown mode the ic will stop switching, the input disconnect switch is open, and the leds will stop sinking current. to shutdown the ic into low power mode, the user must disable the ic using the pwm pin, by keeping the pin low for a period of 32,750 clock cycles. if the fset/sync pin is released at any time after 7 s, the a8521 will proceed to soft start. figure 9. transition of the sw waveform when the sync pulse is detected. the a8521 switching at 2 mhz, applied sync pulse at 1 mhz; shows v out (ch1, 20 v/div.), i out (ch2, 200 ma/div.), fset/sync (ch3, 2 v/div.), and sw node (ch4, 20 v/div.), time = 5 s/div. figure 8. diagram showing a synchronized fset/sync pin and switch node; shows v out (ch1, 20 v/div.), i out (ch2, 200 ma/div.), fset/sync (ch3, 2 v/div.), and sw node (ch4, 20 v/div.), time = 2 s/div. t sw node 2 mhz operation 1 mhz operation fset/sync i out v out c1 c3 c4 c2 150 ns 150 ns t = 454 ns 154 ns t pwsyncon t pwsyncoff figure 10. sync pulse on and off time requirements. t sw node fset/sync i out v out c1 c3 c4 c2
wide input voltage range, high efficiency fault tolerant led driver a8521 15 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com led current setting and led dimming the maximum led current can be up to 80 ma per channel, and is set through the iset pin. to set the i led current, connect a resistor, r iset , between this pin and ground, according to the following formula: r iset = (1.003 653) / i led (2) where i led is in a and r iset is in . this sets the maximum cur- rent through the leds, referred to as the 100% current . standard r iset values, at gain equals 653, are as follows: standard closest r iset resistor value (k ) led current per led, i led (ma) 8.25 80 10.2 65 16.5 40 22.1 30 pwm dimming the led current can be reduced from the 100% current level by pwm dimming using the pwm/en pin. when the pwm/en pin is pulled high, the a8521 turns on and all enabled leds sink 100% current. when pwm/en is pulled low, the boost converter and led sinks are turned off. the compensation (comp) pin is floated, and critical internal circuits are kept active. the typical pwm dimming frequencies fall between 200 hz and 1 khz. fig- ures 11a to 11d provide examples of pwm switching behavior. figure 11a. typical pwm diagram showing v out , i led , and comp pin as well as the pwm signal. pwm dimming frequency is 500 hz at 50% duty cycle; shows v out (ch1, 10 v/div.), comp (ch2, 2 v/div.), pwm (ch3, 5 v/div.), and i led (ch4, 50 ma/div.), time = 500 s/div. figure 11b. typical pwm diagram showing v out , i led , and comp pin as well as the pwm signal. pwm dimming frequency is 500 hz at 1% duty cycle ; shows v out (ch1, 10 v/div.), comp (ch2, 2 v/div.), pwm (ch3, 5 v/div.), and i led (ch4, 50 ma/div.), time = 500 s/div. figure 11c. delay from rising edge of pwm signal to led current; shows pwm (ch1, 2 v/div.), and i led (ch2, 50 ma/div.), time = 200 ns/div. figure 11d. delay from falling edge of pwm signal to led current turn off; shows pwm (ch1, 2 v/div.), and i led (ch2, 50 ma/div.), time = 200 ns/div. t i led pwm c1 c2 t i led pwm comp v out c1 c3 c4 c2 t i led pwm comp v out c1 c3 c4 c2 t i led pwm c1 c2
wide input voltage range, high efficiency fault tolerant led driver a8521 16 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com another important feature of the a8521 is the pwm signal to led current delay. this delay is typically less than 500 ns, which allows greater accuracy at low pwm dimming duty cycles, as shown in figure 12. apwm pin the apwm pin is used in conjunction with the iset pin (see fig- ure 13). this is a digital signal pin that internally adjusts the iset current. when this pin is not used it should be tied to ground. the typical input signal frequency is between 20 khz and 1 mhz. the duty cycle of this signal is inversely proportional to the per- centage of current that is delivered to the leds (figure 14). to use this pin for a trim function, the user should set the maxi- mum output current to a value higher than the required current by at least 5%. the led i set current is then trimmed down to the appropriate value. another consideration that also is important is the limitation of the user apwm signal duty cycle. in some cases it might be preferable to set the maximum i set current to be 25% to 50% higher, thus allowing the apwm signal to have duty cycles that are between 25% and 50%. figure 13. simplified block diagram of the apwm and iset circuit. figure 14. output current versus duty cycle; 200 khz apwm signal. figure 15. percentage error of the led current versus pwm duty cycle; 200 khz apwm signal. apwm current adjust iset current mirror led driver iset r iset pwm a8521 0 10 20 30 40 50 60 70 80 0 20406080100 i out (ma) apwm duty cycle (%) i out = 80 ma i out = 65 ma apwm duty cycle (%) 0 2 4 6 8 10 12 0 20406080100 %err led i out = 80 ma i out = 65 ma figure 12. typical percentage error, due to pwm-to-led delay, for the average led current versus pwm duty cycle (at 200 hz pwm frequency). 10 8 6 4 2 0 err led (%) pwm duty cycle, d (%) 0.1 1 10 100 worst-case typical
wide input voltage range, high efficiency fault tolerant led driver a8521 17 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 17. diagram showing the transition of led current from 80 ma to 60 ma, when a 25% duty cycle signal is applied to the apwm pin; pwm = 1; shows i led (ch1, 50 ma/div.), apwm (ch2, 10 v/div.), and pwm/en (ch3, 5 v/div.), time = 500 s/div. figure 16. diagram showing the transition of led current from 60 ma to 80 ma, when a 25% duty cycle signal is removed from the apwm pin. pwm = 1; shows i led (ch1, 50 ma/div.), apwm (ch2, 10 v/div.), and pwm/en (ch3, 5 v/div.), time = 500 s/div. t i led apwm pwm/en c1 c3 c2 as an example, a system that delivers a full led current of 80 ma per led would deliver 60 ma of current per led when an apwm signal is applied with a duty cycle of 25% (figures 16 and 17). although the order in which apwm and the pwm signal are enabled does not matter, when enabling the a8521 into low cur- rent output while pwm and apwm dimming, the apwm signal should be enable before or at the same time as the pwm signal. this sequence will prevent the light output intensity from chang- ing during power up of the ic. figure 18 shows the sequencing of the apwm and pwm signal during power-up to prevent inadvertent light intensity changes. the full intensity light output with no apwm or pwm dimming is 80 ma per channel. figure 19. transition of output current level when a 50% duty cycle signal is applied to the apwm pin, in conjunction with a 50% duty cycle pwm dimming being applied to the pwm pin; shows i out (ch1, 50 ma/div.), apwm (ch2, 10 v/div.), and pwm/en (ch3, 5 v/div.), time = 500 s/div. t i out apwm pwm/en c1 c3 c2 figure 18. diagram showing power-up sequencing led current of 5 ma per channel with a 10% duty cycle pwm signal and a 95% duty cycle apwm signal; shows apwm (ch1, 5 v/div.), i led (ch2, 50 ma/div.), pwm/en (ch3, 5 v/div.), and v out (ch4, 10 v/div.), time = 500 s/div. t i led apwm pwm/en v out c1 c4 c3 c2 t i led apwm pwm/en c1 c3 c2
wide input voltage range, high efficiency fault tolerant led driver a8521 18 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com although the apwm dimming function has a wide frequency range, if this function is used strictly as an analog dimming function it is recommended to use frequency ranges between 50 and 500 khz for best accuracy. the frequency range must be considered only if the user is not using this function as a closed loop trim function. another limitation is that the propagation delay between this apwm signal and i out takes several milli- seconds to change the actual led current. this effect is shown in figures 16, 17, and 19. analog dimming the a8521 can also be dimmed by using an external dac or another voltage source applied either directly to the ground side of the r iset resistor or through an external resistor to the iset pin (see figure 19). the limit of this type of dimming depends on the range of the iset pin. in the case of the a8521 the limit is 20 to 125 a. ? for a single resistor (panel a of figure 20), the iset current is controlled by the following formula: i set = v iset ? v dac r iset (3) where v iset is the iset pin voltage and v dac is the dac output voltage. when the dac voltage is 0 v the led current will be at its maximum. to keep the internal gain amplifier stable, the user should not decrease the current through the r iset resistor to less than 20 a ? for a dual-resistor configuration (panel b of figure 20), the i set current is controlled by the following formula: i set = ? v iset r iset v dac ? v iset r 1 (4) the advantage of this circuit is that the dac voltage can be higher or lower, thus adjusting the led current to a higher or lower value of the preset led current set by the r iset resistor: ? v dac = 1.003 v; the output is strictly controlled by r iset ? v dac > 1.003 v; the led current is reduced ? v dac < 1.003 v; the led current is increased figure 20. simplified diagrams of voltage control of i led : typical applications using a dac to control i led using a single resistor (upper), and dual resistors (lower). gnd dac vdac gnd a8521 iset gnd dac vdac gnd a8521 iset r iset r1 r iset (a) (b)
wide input voltage range, high efficiency fault tolerant led driver a8521 19 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com t v out pwm sw node output disconnect event detected i out c1 c3 c4 c2 overvoltage protection the a8521 has overvoltage protection (ovp) and open schottky diode (d1 in figure 1) protection. the ovp protection has a default level of 8.1 v and can be increased up to 53 v by con- necting resistor r ovp between the ovp pin and v out . when the current into the ovp pin exceeds 199 a (typical), the ovp comparator goes low and the boost stops switching. the following equation can be used to determine the resistance for setting the ovp level: r ovp = ( v outovp ? v ovp(th) ) / i ovph (5) where: v outovp is the target overvoltage level, r ovp is the value of the external resistor, in , v ovp(th) is the pin ovp trip point found in the electrical charac- teristics table, and i ovph is the current into the ovp pin. there are several possibilities for why an ovp condition would be encountered during operation, the two most common being: a disconnected output, and an open led string. examples of these are provided in figures 21 and 22. figure 21 illustrates when the output of the a8521 is discon- nected from load during normal operation. the output voltage instantly increases up to ovp voltage level and then the boost stops switching to prevent damage to the ic. if the output is drained off, eventually the boost might start switching for a short duration until the ovp threshold is hit again. figure 22 displays a typical ovp event caused by an open led string. after the ovp condition is detected, the boost stops switching, and the open led string is removed from operation. afterwards v out is allowed to fall, and eventually the boost will resume switching and the a8521 will resume normal operation. figure 21. ovp protection in an output disconnect event; shows v out (ch1, 10 v/div.), sw node (ch2, 50 v/div.), pwm (ch3, 5 v/div.), and i out (ch4, 200 ma/div.), time = 1 ms/div. figure 22. ovp protection in an open led string event; shows v out (ch1, 10 v/div.), sw node (ch2, 50 v/div.), pwm (ch3, 5 v/div.), and i out (ch4, 200 ma/div.), time = 500 s/div. t v out pwm sw node i out c1 c3 c4 c2 led string open condition detected
wide input voltage range, high efficiency fault tolerant led driver a8521 20 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com a8521 also has built-in secondary overvoltage protection to protect the internal switch in the event of an open diode condi- tion. open schottky diode detection is implemented by detecting overvoltage on the sw pin of the device. if voltage on the sw pin exceeds the device safe operating voltage rating, the a8521 disables and remains latched. to clear this fault, the ic must be shut down either by using the pwm/en signal or by going below the uvlo threshold on the vin pin. figure 23 illustrates this. as soon as the switch node voltage (sw) exceeds 60 v, the ic shuts down. due to small delays in the detection circuit, as well as there being no load present, the switch node voltage will rise above the trip point voltage. figure 24 illustrates when the a8521 is being enabled during an open diode condition. the ic goes through all of its initial led detection and then tries to enable the boost, at which point the open diode is detected. figure 23. ovp protection in an open schottky diode event, while the ic is in normal operation; shows pwm (ch1, 5 v/div.), sw node (ch2, 50 v/div.), v out (ch3, 20 v/div.), and i out (ch4, 200 ma/div.), time = 1 s/div. figure 24. ovp protection when the ic is enabled during an open diode condition; shows pwm (ch1, 5 v/div.), sw node (ch2, 50 v/div.), v out (ch3, 10 v/div.), and i out (ch4, 200 ma/div.), time = 500 s/div. t v out pwm sw node open diode condition detected i out c1 c3 c4 c2 t v out pwm sw node open diode condition detected i out c1 c3 c4 c2
wide input voltage range, high efficiency fault tolerant led driver a8521 21 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 25. normal operation of the switch node (sw); inductor current (i l ) and output voltage (v out ) for 9 series leds in each of four strings configuration; shows sw node (ch1, 20 v/div.), inductor current i l (ch2, 1 a/div.), v out (ch3, 10 v/div.), and pwm/en (ch4, 5 v/div.), time = 2 s/div. figure 26. cycle-by-cycle current limiting; inductor current (yellow trace, i l ), note reduction in output voltage as compared to normal operation with the same configuration (figure 26); shows sw node (ch1, 20 v/div.), inductor current i l (ch2, 1 a/div.), v out (ch3, 10 v/div.), and pwm/en (ch4, 5 v/div.), time = 2 s/div. figure 27. secondary boost switch current limit; when this limit is hit, the a8521 immediately shuts down; shows pwm (ch1, 5 v/div.), v out (ch2, 5 v/div.), sw node (ch3, 50 v/div.), and inductor current i l (ch4, 2 a/div.), time = 100 ns/div. t v out pwm/en sw node i l c1 c3 c4 c2 t v out pwm/en sw node i l c1 c3 c4 c2 t i l pwm/en sw node c1 c3 c4 c2 fault boost switch overcurrent protection the boost switch is protected with cycle-by-cycle current limiting set at a minimum of 3.0 a. there is also a secondary current limit that is sensed on the boost switch. when detected this current limit immediately shuts down the a8521. the level of this cur- rent limit is set above the cycle-by-cycle current limit to protect the switch from destructive currents when the boost inductor is shorted. various boost switch overcurrent conditions are shown in figures 25 through 27.
wide input voltage range, high efficiency fault tolerant led driver a8521 22 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com input overcurrent protection and disconnect switch the primary function of the input disconnect switch is to protect the system and the device from catastrophic input currents during a fault condition. the external circuit implementing the discon- nect is shown in figure 28. if the input disconnect switch is not used, the vsense pin must be tied to vin and the gate pin must be left open. when selecting the external pmos, check for the following parameters: ? drain-source breakdown voltage v (br)dss > ?40 v ? gate threshold voltage (make sure it is fully conducting at v gs = ?4 v, and cut-off at ?1 v) ? r ds(on) : make sure the on-resistance is rated at v gs = ?4.5 v or similar, not at ?10 v; derate it for higher temperature the input disconnect switch has two modes of operation: ? 1x mode when the input current is between one and two times the preset current limit value, the disconnect switch enters a con- stant-current mode for a maximum duration of 10,000 cycles or 5 ms at 2 mhz. during this time, the fault flag is set immediately and the disconnect switch goes into a linear mode of operation, in which the input current will be limited to a value approximate to the 1x current trip point level (figure 29). if the fault corrects itself before the expiration of the timer, the fault flag will be removed and normal operation will resume. the user can also during this time decide whether to shut down the a8521. to immediately shut down the device, pull the fset/ sync pin low for more than 7 s. after the fset/sync pin has been low for a period longer than 7 s, the ic will stop switching, the input disconnect switch will open, and the ledx pins will stop sinking current. the a8521 can be powered-down into low power mode. to do so, disable the ic by keeping the pwm/en pin low for a period of 32,750 clock cycles. to keep the discon- nect switch stable while the disconnect switch is in 1x mode, use a 22 nf capacitor for c c and a 20 resistor for r c . figure 28. typical circuit showing the implementation of the input disconnect feature. gate r adj r c c c r sc to l 1 vsense vin a8521 q1 v in figure 29. showing typical wave forms for a 3-a, 1x current limit under a fault condition; shows f sw = 800 khz, f a u l t (ch1, 5 v/div.), i in (ch2, 2 a/ div.), gate (ch3, 5 v/div.), and pwm/en (ch4, 5 v/div.), time = 5 ms/div. t gate pwm/en i in c1 c3 c4 c2 fault (1) initial fault detected (2) disconnect switch goes into a linear mode (4) after 12.5 ms, disconnect switch shuts down (3) i in limited to 3 a figure 30. 2x mode, secondary overcurrent fault condition. i in is the input current through the switch. the fault flag is set at the 1x current limit, and when the 2x current limit is reached the a8521 disables the gate of the disconnect switch (gate); shows f a u l t (ch1, 5 v/div.), gate (ch2, 10 v/div.), i in (ch3, 2 a/div.), and pwm/en (ch4, 5 v/div.), time = 5 s/div. t gate pwm/en i in c1 c3 c4 c2 fault fault flag set at 1x trip point a8521 shuts down at 2x trip point
wide input voltage range, high efficiency fault tolerant led driver a8521 23 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com ? 2x current limit if the input current level goes above 2x of the preset current limit threshold, the a8521 will shut down in less than 3 s regardless of user input (figure 30). this is a latched condition. the fault flag is also set to indicate a fault. this feature is meant to prevent catastrophic failure in the system due to inductor short to ground, switch pin short to ground, or output short to ground. setting the current sense resistor the typical threshold for the current sense circuit is 104 mv, when r adj is 0 . this voltage can be trimmed by the r adj resistor. the typical 1x trip point should be set at about 3 a, which coincides with the cycle-by-cycle current limit minimum threshold. for example, given 3 a of input current, and the calculated maxi- mum value of the sense resistor, r sc = 0.033 . the r sc chosen is 0.03 , a standard. also: r adj = ( v sensetrip ? v adj ) / i adj (6) the trip point voltage is calculated as: v adj = 3.0 a 0.03 = 0.090 v r adj = (0.104 ? 0.09 v) / (20.3 a) = 731 input uvlo when v in and v sense rise above the v uvlorise threshold, the a8521 is enabled. a8521 is disabled when v in falls below the v uvlofall threshold for more than 50 s. this small delay is used to avoid shutting down because of momentary glitches in the input power supply. when v in falls below 4.35 v, the ic will shut down (see figure 31). vdd the vdd pin provides regulated bias supply for internal circuits. connect the capacitor c vdd with a value of 0.1 f or greater to this pin. the internal ldo can deliver no more than 2 ma of cur- rent with a typical v dd of about 3.5 v, enabling this pin to serve as the pull-up voltage for the f a u l t pin. shutdown if the pwm/en pin is pulled low for more than t pwml (32,750 clock cycles), the device enters shutdown mode and clears all figure 31. shutdown showing a falling input voltage (v in ); shows v in (ch1, 2 v/div.), i out (ch2, 200 ma/div.), v dd (ch3, 5 v/div.), and pwm/en (ch4, 2 v/div.), time = 5 ms/div. figure 32. shutdown using the enable function, showing the 16 ms delay between the pwm/en signal and when the vdd and gate of the disconnect switch turns off; shows gate (ch1, 10 v/div.), i out (ch2, 200 ma/div.), v dd (ch3, 5 v/div.), and pwm/en (ch4, 2 v/div.), time = 5 ms/div. t i out pwm/en v in v dd c1 c2 c3 c4 t i out pwm/en gate v dd c2 c1 c3 c4
wide input voltage range, high efficiency fault tolerant led driver a8521 24 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com internal fault registers. as an example, at a 2 mhz clock fre- quency, it will take approximately 16.3 ms to shut down the ic into the low power mode (figure 32). when the a8521 is shut down, the ic will disable all current sources and wait until the pwm/en signal goes high to re-enable the ic. if faster shut down is required, the fset/sync pin can be used. fault protection during operation the a8521 constantly monitors the state of the system to deter- mine if any fault conditions occur during normal operation. the response to a triggered fault condition is summarized in the fault mode table. the possible fault conditions that the device can detect are: open led pin, led pin shorted to ground, shorted inductor, v out short to ground, sw pin shorted to ground, iset pin shorted to ground, and input disconnect switch source shorted to ground. note the following: ? some of the protection features might not be active during startup, to prevent false triggering of fault conditions. ? some of these faults will not be protected if the input disconnect switch is not being used. an example of this is v out short to ground. fault mode table fault name type active fault flag set description boost disconnect switch sink driver primary switch overcurrent protection (cycle-by-cycle current limit) auto-restart always no this fault condition is triggered by the cycle-by- cycle current limit, i sw(lim) . off for a single cycle on on secondary switch current limit latched always yes when the current through the boost switch exceeds secondary current sw limit (i sw(lim2) ) the device immediately shuts down the disconnect switch, led drivers, and boost. the fault flag is set. to re- enable the device, the pwm/en pin must be pulled low for 32,750 clock cycles. off off off input disconnect current limit latched always yes the device is immediately shut off if the voltage across the input sense resistor is 2x the preset current value. the fault flag is set. if the input current limit is between 1x and 2x, the fault flag is set but the ic will continue to operate normally for t gfault1 or until it is shut down. to re-enable the device the pwm/en pin must be pulled low for 32,750 clock cycles. off off off secondary ovp latched always yes secondary overvoltage protection is used for open diode detection. when diode d1 opens, the sw pin voltage will increase until v ovp(sec) is reached. this fault latches the ic. the input disconnect switch is disabled as well as the led drivers, and the fault flag is set. to re-enable the part the pwm pin must be pulled low for 32,750 clock cycles. off off off continued on the next page?
wide input voltage range, high efficiency fault tolerant led driver a8521 25 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com fault mode table (continued) fault name type active fault flag set description boost disconnect switch sink driver led pin short protection auto-restart startup no this fault prevents the device from starting-up if either of the ledx pins are shorted. the device stops soft-start from starting while either of the ledx pins are determined to be shorted. after the short is removed, soft-start is allowed to start. off on off led pin open auto-restart normal operation no when an ledx pin is open the device will determine which led pin is open by increasing the output voltage until ovp is reached. any led string not in regulation will be turned off. the device will then go back to normal operation by reducing the output voltage to the appropriate voltage level. on on off for open pins. on for all others. iset short protection auto-restart always no this fault occurs when the iset current goes above 150% of the maximum current. the boost will stop switching, the disconnect switch will turn off, and the ic will disable the led sinks until the fault is removed. when the fault is removed the ic will try to to regulate to the preset led current. off on off fset/sync short protection auto-restart always yes fault occurs when the fset/sync current goes above 150% of maximum current, about 180 a. the boost will stop switching, the disconnect switch will turn off, and the ic will disable the led sinks until the fault is removed. when the fault is removed the ic will try to restart with soft-start. off off off overvoltage protection auto-restart always no fault occurs when ovp pin exceeds v ovp(th) threshold. the a8521 will immediately stop switching to try to reduce the output voltage. if the output voltage decreases then the a8521 will restart switching to regulate the output voltage. stop during ovp event. on on overtemperature protection auto-restart always no fault occurs when the die temperature exceeds the overtemperature threshold, 165c. off off off vin uvlo auto-restart always no fault occurs when v in drops below v uvlo , 3.90 v maximum. this fault resets all latched faults. off off off
wide input voltage range, high efficiency fault tolerant led driver a8521 26 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com design example for boost configuration this section provides a method for selecting component values when designing an application using the a8521. the resulting design is diagrammed in figure 33. assumptions: for the purposes of this example, the following are given as the application requirements: ? v bat : 10 to 14 v ? quantity of led channels, # channels : 4 ? quantity of series leds per channel, # seriesleds : 10 ? led current per channel, i led : 60 ma ? v f at 60 ma: 3.2 v ? f sw : 2 mhz ? t a (max): 65c ? pwm dimming frequency: 200 hz, 1% duty cycle procedure: the procedure consists of selecting the appropriate configuration and then the individual component values, in an ordered sequence. step 1 connect leds to pins led1 and led2. step 2 determining the led current setting resistor r iset : r iset = ( v iset a iset ) / i led (7) = (1.003 (v) 653) / 60 ma = 10.92 k choose a 11.00 k resistor. step 3 determining the ovp resistor. the ovp resistor is connected between the ovp pin and the output voltage of the converter. step 3a the first step is determining the maximum voltage based on the led requirements. the regulation voltage, v led , of the a8521 is 700 mv. a constant term, 2 v, is added to give margin to the design due to noise and output voltage ripple. v out(ovp) = # seriesleds v f + v led + 2 (v) (8) = 10 3.2 v+ 0.7 v + 2 v = 34.7 v then the ovp resistor is: r ovp = ( v out(ovp) ? v ovp(th) ) / i ovph (9) = (34.7 (v) ? 8.1 (v)) / 199 ( a) = 133.67 k where both i ovph and v ovp(th) are taken from the electrical characteristics table. chose a value of resistor that is higher value than the calculated r ovp . in this case a value of 137 k was selected. below is the actual value of the minimum ovp trip level with the selected resistor: v out(ovp) = 137 (k ) 199 ( a) + 8.1 (v) = 35.36 v step 3b at this point a quick check must be done to see if the conversion ratio is acceptable for the selected frequency. d maxofboost = 1 ? t swofftime f sw (10) = 1 ? 68 (ns) 2.0 (mhz) = 86.4% where the minimum off-time (t swofftime ) is found in the electri- cal characteristics table. the theoretical maximum v out is then calculated as: v out (max) v d =? 1 ? d maxofboost v in (min) 0.4 (v) 73.13 v == ? 1 ? 0.864 10 (v) (11) where v d is the diode forward voltage. the theoretical maximum v out value must be greater than the value v out(ovp) . if this is not the case, the switching frequency of the boost converter must be reduced to meet the maximum duty cycle requirements. step 4 selecting the inductor. the inductor must be chosen such that it can handle the necessary input current. in most applica- tions, due to stringent emi requirements, the system must operate in continuous conduction mode throughout the whole input volt- age range. application information
wide input voltage range, high efficiency fault tolerant led driver a8521 27 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com step 4a determining the duty cycle, calculated as follows: d (max) v d = + v in (min) v out(ovp) 72.04% == 35.36 (v) + 0.4 (v) 1 ? 1 ? 10 (v) (12) step 4b determining the maximum and minimum input current to the system. the minimum input current will dictate the induc- tor value. the maximum current rating will dictate the current rating of the inductor. first, the maximum input current, given: i out = # channels i led 0.240 a == 4 0.060 (a) (13) then: i in (max) = v in (min) v out(ovp) i out h 0.94 a == 35.36 (v) 10 (v) 0.90 240 (ma) (14) where is efficiency. next, calculate minimum input current, as follows: i in (min) = v in (max) v out(ovp) i out h 0.67 a == 35.36 (v) 14 (v) 0.90 240 (ma) (15) a good approximation of efficiency, , can be taken from the efficiency curves located in the datasheet. a value of 90% is a good starting approximation. step 4c determining the inductor value. to ensure that the inductor operates in continuous conduction mode, the value of the inductor must be set such that the ? inductor ripple current is not greater than the average minimum input current. a first past assumes i ripple to be 40% of the maximum inductor current: i l = i in (max) i ripple (16) = 0.94 0.40 = 0.376 a then: l = v in (min) d (max) f sw i l 9.57 h 0.376 (a) = = 0.72 10 (v) 2 (mhz) (17) step 4d double-check to make sure the ? current ripple is less than i in (min): i in (min) > 1 / 2 i l (18) 0.67 a > 0.19 a a good inductor value to use would be 10 h. step 4e this step is used to verify that there is sufficient slope compensation for the inductor chosen. the slope compensation value is determined by the following formula: 2 10 6 slope compensation == f sw 3.6 3.6 a / s (19) next insert the inductor value used in the design: = v in (min) d (max) f sw l used i lused 10 ( h) 0.36 a == 0.72 10 (v) 2.0 (mhz) (20) calculate the minimum required slope: = (1 ? d (max)) (1 ? 0.72) f sw required slope (min) i lused 0.36 (a) 1 1 1 10 ? 6 110 ? 6 == 2.57 a/ s 2.0 (mhz) (21) if the minimum required slope is greater than the calculated slope compensation, the inductor value must be increased. note: the slope compensation value is in a/ s, and 1 10 ?6 is a constant multiplier. step 4f determining the inductor current rating. the inductor current rating must be greater than the i in (max) value plus the ripple current i l , calculated as follows: l (min) = i in (max) + 1 / 2 i lused (22) = 0.94 (a) + 0.36 (a) / 2 = 1.12 a step 5 determining the resistor value for a particular switching frequency. use the r fset values shown in figure 7. for example, a 10 k resistor will result in a 2 mhz switching frequency. step 6 choosing the proper switching diode. the switching diode must be chosen for three characteristics when it is used in led lighting circuitry. the most obvious two are: current rating of the diode and reverse voltage rating.
wide input voltage range, high efficiency fault tolerant led driver a8521 28 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the reverse voltage rating should be such that during operation condition, the voltage rating of the device is larger than the maxi- mum output voltage. in this case it is v out(ovp) . the peak current through the diode is calculated as: i dp = i in (max) + 1 / 2 i lused (23) = 0.94 (a) + 0.36 (a) / 2 = 1.12 a the third major component in deciding the switching diode is the reverse current, i r , characteristic of the diode. this characteristic is especially important when pwm dimming is implemented. during pwm off-time the boost converter is not switching. this results in a slow bleeding off of the output voltage, due to leakage currents. i r can be a large contributor, especially at high tempera- tures. on the diode that was selected in this design, the current varies between 1 and 100 a. step 7 choosing the output capacitors. the output capacitors must be chosen such that they can provide filtering for both the boost converter and for the pwm dimming function. the biggest factors that contribute to the size of the output capacitor are: pwm dimming frequency and pwm duty cycle. another major contributor is leakage current, i lk . this current is the combina- tion of the ovp leakage current as well as the reverse current of the switching diode. in this design the pwm dimming frequency is 200 hz and the minimum duty cycle is 1%. typically, the volt- age variation on the output, v cout , during pwm dimming must be less than 250 mv, so that no audible hum can be heard. the capacitance can be calculated as follows: c out = f pwm(dimming) 1 ? d (min) 1 ? 0.01 200 hz i lk 200 a 3.96 f == 0.250 v v cout (24) a capacitor larger than 3.96 f should be selected due to degra- dation of capacitance at high voltages on the capacitor. a ceramic 4.7 f 50 v capacitor is a good choice to fulfill this requirement. corresponding capacitors include: vendor value part number murata 4.7 f 50 v grm32er71h475ka88l murata 2.2 f 50 v grm31cr71h225ka88l the rms current through the capacitor is given by: i cout rms = 1 ? d (max) d (max) + ? i lused i out 0.240 (a) 0.39 a 12 == i in (max) 1 ? 0.72 0.72 + 0.36 (a) 0.94 (a) 12 (25) the output capacitor must have a current rating of at least 390 ma. the capacitor selected in this design was a 4.7 f 50 v capacitor with a 3 a current rating. step 8 selecting input capacitor. the input capacitor must be selected such that it provides a good filtering of the input voltage waveform. a good rule of thumb is to set the input voltage ripple v in to be 1% of the minimum input voltage. the minimum input capacitor requirements are as follows: c in = f sw 0.36 (a) ? i lused 0.23 f 8 == ? v in 2 (mhz) 0.1 (v) 8 (26) the rms current through the capacitor is given by: c in rms = (1 ? d ) i out ? i lused 0.095 a 12 = = i in (max) (1 ? 0.72) 0.240 (a) 0.36 (a) 0.94 (a) 12 (27) a good ceramic input capacitor with ratings of 2.2 f 50 v or 4.7 f 50 v will suffice for this application. corresponding capacitors include: vendor value part number murata 4.7 f 50 v grm32er71h475ka88l murata 2.2 f 50 v grm31cr71h225ka88l
wide input voltage range, high efficiency fault tolerant led driver a8521 29 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com step 9 choosing the input disconnect switch components. set the input disconnect 1x current limit to 3 a by choosing a sense resistor. the calculated maximum value of the sense resistor is: r sc (max) = v sensetrip / 3.0 (a) (28) = 0.104 (v) / 3.0 (a) = 0.035 the r sc chosen is 0.033 , a standard. the trip point voltage must be: v adj = 3.0 (a) 0.033 ( ) = 0.099 (v) r adj = ( v sensetrip ? v adj ) / i adj (typ) (29) r adj = (0.104 (v) ? 0.099 (v)) / 20.3 ( a) = 246.31 a value of 249 was chosen for this design. gate sw q1 l1 d1 c vdd ovp v out r ovp c out r sc r adj vsense vin vdd pwm/en apwm iset fset/sync agnd pgnd comp c p r z c z fault pad a8521 150 v c 10 h 2 a / 60 v 137 k 0.033 249 100 k r iset 11 k r fset 10 k 4.7 f c in 4.7 f c c 22 nf r c 20 0.1 f 0.47 f 120 pf v in 10 to 14 v led4 led1 10 leds each string led2 led3 figure 33. the schematic diagram showing calculated values from the design example above.
wide input voltage range, high efficiency fault tolerant led driver a8521 30 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com design example for sepic configuration this section provides a method for selecting component values when designing an application using the a8521 in sepic (sin- gle-ended primary-inductor converter) circuit. sepic topology has the advantage that it can generate a positive output voltage either higher or lower than the input voltage. the resulting design is diagrammed in figure 34. assumptions: for the purposes of this example, the following are given as the application requirements: ? v bat : 6 to 14 v ( v in (min): 5 v and v in (max): 16 v ) ? quantity of led channels, # channels : 4 ? quantity of series leds per channel, # seriesleds : 4 ? led current per channel, i led : 60 ma ? led v f at 60 ma: 3.3 v ? f sw : 2 mhz ? t a (max): 65c ? pwm dimming frequency: 200 hz, 1% duty cycle procedure: the procedure consists of selecting the appropriate configuration and then the individual component values, in an ordered sequence. step 1 connecting leds to ledx pins. if only some of the led channels are needed, the unused ledx pins should be pulled to ground using a 1.5 k resistor. step 2 determining the led current setting resistor r iset : r iset = ( v iset a iset ) / i led (30) = (1.003 (v) 653) / 0.60 (a) = 10.92 k choose an 11.00 k 1% resistor. step 3 determining the ovp resistor. the ovp resistor is connected between the ovp pin and the output voltage of the converter. step 3a the first step is determining the maximum voltage based on the led requirements. the regulation voltage, v led , of the a8521 is 700 mv. a constant term, 2 v, is added to give margin to the design due to noise and output voltage ripple. v out(ovp) = # seriesleds v f + v led + 2 (v) (31) = 4 3.3 (v) + 0.7 (v) + 2 (v) = 15.9 v then the ovp resistor is: r ovp = ( v out(ovp) ? v ovp(th) ) / i ovph (32) = (15.9 (v) ? 8.1 (v)) / 0.199 (ma) = 39.196 k where both i ovph and v ovp(th) are taken from the electrical characteristics table. in this case a value of 39.2 k was selected. below is the actual value of the minimum ovp trip level with the selected resistor: v out(ovp) = 39.2 (k ) 0.199 (ma) + 8.1 (v) = 15.9 v step 3b at this point a quick check must be done to determine if the conversion ratio is acceptable for the selected frequency. d max = 1 ? t swofftime f sw (33) = 1 ? 68 (ns) 2 (mhz) = 86.4% where the minimum off-time (t swofftime ) is found in the electri- cal characteristics table. the theoretical maximum v out is then calculated as: v out (max) = v d ? 1 ? d max d max v in (min) 0.4 (v) 30.3 v == ? 1 ? 0.86 0.86 5 (v) (34) where v d is the diode forward voltage. the theoretical maximum v out value must be greater than the value v out(ovp) . if this is not the case, it may be necessary to reduce the frequency to allow the boost to convert the volt- age ratios. step 4 selecting the inductor. the inductor must be chosen such that it can handle the necessary input current. in most applica-
wide input voltage range, high efficiency fault tolerant led driver a8521 31 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com tions, due to stringent emi requirements, the system must operate in continuous conduction mode throughout the whole input volt- age range. step 4a determining the duty cycle, calculated as follows: d (max) v d = + v d + v out(ovp) + v in (min) v out(ovp) 76.5% == 5 (v) + 15.9 (v) + 0.4 (v) + 0.4 (v) 15.9 (v) (35) step 4b determining the maximum and minimum input current to the system. the minimum input current will dictate the induc- tor value. the maximum current rating will dictate the current rating of the inductor. first, the maximum input current, given: i out = # channels i led 0.240 a == 4 0.060 (a) (36) then: i in (max) = v in (min) v out(ovp) i out h 0.848 a == 15.9 (v) 5 (v) 0.90 0.24 (a) (37) where is efficiency. next, calculate minimum input current, as follows: i in (min) = v in (max) v out(ovp) i out h 0.265 a == 15.9 (v) 16 (v) 0.90 0.24 (a) (38) step 4c determining the inductor value. to ensure that the induc- tor operates in continuous conduction mode, the value of the inductor must be set such that the ? inductor ripple current is not greater than the average minimum input current. as a first pass assume i ripple to be 30% of the maximum inductor current: i l = i in (max) i ripple (39) = 0.848 0.30 = 0.254 a then: l = v in (min) d (max) f sw i l 7.53 h 0.254 (a) = = 0.765 5 (v) 2 (mhz) (40) step 4d double-check to make sure the ? current ripple is less than i in (min): i in (min) > 1 / 2 i l (41) 0.265 a > 0.127 a a good inductor value to use would be 10 h. step 4e next insert the inductor value used in the design to deter- mine the actual inductor ripple current: = v in (min) d (max) f sw l used i lused 10 ( h) 0.191 a == 0.765 5 (v) 2.0 (mhz) (42) step 4f determining the inductor current rating. the inductor current rating must be greater than the i in (max) value plus half of the ripple current i l , calculated as follows: l (min) = i in (max) + 1 / 2 i lused (43) = 0.848 (a) + 0.096 (a) = 0.944 a step 5 determining the resistor value for a particular switching frequency. use the r fset values shown in figure 7. for example, a 10 k resistor will result in a 2 mhz switching frequency. step 6 choosing the proper switching diode. the switching diode must be chosen for three characteristics when it is used in led lighting circuitry. the most obvious two are: current rating of the diode and reverse voltage rating.
wide input voltage range, high efficiency fault tolerant led driver a8521 32 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the reverse breakdown voltage rating for the output diode in a sepic circuit should be: v bd > v out(ovp) (max) + v in (max) (44) > 15.9 (v) + 16 (v) = 31.9 v because the maximum output voltage in this case is v out(ovp) . the peak current through the diode is calculated as: i dp = i in (max) + 1 / 2 i lused (45) = 0.848 (a) + 0.096 (a) = 0.944 a the third major component in deciding the switching diode is the reverse current, i r , characteristic of the diode. this characteristic is especially important when pwm dimming is implemented. during pwm off-time the boost converter is not switching. this results in a slow bleeding off of the output voltage, due to leakage currents. i r can be a large contributor, especially at high tempera- tures. on the diode that was selected in this design, the current varies between 1 and 100 a. it is often advantageous to pick a diode with a much higher breakdown voltage, just to reduce the reverse current. therefore for this example, pick a diode rated for a v bd of 60 v, instead of just 40 v. step 7 choosing the output capacitors. the output capacitors must be chosen such that they can provide filtering for both the boost converter and for the pwm dimming function. the biggest factors that contribute to the size of the output capacitor are: pwm dimming frequency and pwm duty cycle. another major contributor is leakage current, i lk . this current is the combina- tion of the ovp leakage current as well as the reverse current of the switching diode. in this design the pwm dimming frequency is 200 hz and the minimum duty cycle is 1%. typically, the volt- age variation on the output, v cout , during pwm dimming must be less than 250 mv, so that no audible hum can be heard. the capacitance can be calculated as follows: c out = f pwm(dimming) 1 ? d (min) 1 ? 0.01 200 (hz) i lk 200 ( a) 3.96 f == 0.250 (v) v cout (46) a capacitor larger than 3.96 f should be selected due to degra- dation of capacitance at high voltages on the capacitor. select a 4.7 f capacitor for this application. the rms current through the capacitor is given by: i cout rms = 1 ? d (max) d (max) i out 0.240 (a) 0.433 a == 1 ? 0.765 0.765 (47) the output capacitor must have a ripple current rating of at least 500 ma. the capacitor selected for this design is a 4.7 f 50 v capacitor with a 1.5 a current rating. step 8 selecting input capacitor. the input capacitor must be selected such that it provides a good filtering of the input voltage waveform. a estimation rule is to set the input voltage ripple, v in , to be 1% of the minimum input voltage. the minimum input capacitor requirements are as follows: c in = f sw 0.191 (a) ? i lused 0.24 f 8 == ? v in 2 (mhz) 0.05 (v) 8 (48) the rms current through the capacitor is given by: c in rms = ? i lused 0.055 a 12 = = 0.191 (a) 12 (49) a good ceramic input capacitor with a rating of 2.2 f 25 v will suffice for this application.
wide input voltage range, high efficiency fault tolerant led driver a8521 33 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com step 9 selecting coupling capacitor c sw . the minimum capaci- tance of c sw is related to the maximum voltage ripple allowed across it: c sw = f sw 0.24 (a) 0.765 i out d max 0.92 f == ? v sw 2 (mhz) 0.1 (v) (50) the rms current requirement of the coupling capacitor is given by: i csw rms = 1 ? d (max) d (max) i in (max) 0.848 (a) 0.47 a == 1 ? 0.765 0.765 (51) the voltage rating of the coupling capacitor must be greater than v in (max), or 16 v in this case. a ceramic capacitor rated for 2.2 f 25 v will suffice for this application. figure 34. typical application showing sepic configuration, with accurate input current sense, and vsense to ground protection. gate sw q1 2.2 f 2.2 f 4.7 f 0.47 f 120 pf 10 h 10 h 22 nf 0.1 f 100 k 10 k 150 11 k 20 39.2 k 249 0.033 l1 2 a / 60 v d1 c vdd ovp v out c out r sc r adj vsense vin vdd pwm/en apwm iset fset/sync agnd pgnd comp c p r z c z fault led4 led1 led2 led3 pad a8521 v c r iset r fset c in c c r c v in 9 to 16 v c sw l2 r ovp
wide input voltage range, high efficiency fault tolerant led driver a8521 34 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package lp, 20-pin tssop with exposed thermal pad a 1.20 max 0.15 0.00 0.30 0.19 0.20 0.09 8o 0o 0.60 0.15 1.00 ref c seating plane c 0.10 20x 0.65 bsc 0.25 bsc 2 1 20 6.500.10 4.400.10 3.00 3.00 4.12 4.12 6.400.20 gauge plane seating plane a terminal #1 mark area for reference only; not for tooling use (reference mo-153 act) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown b 0.45 1.70 20 2 1 pcb layout reference view b 6.10 0.65 c exposed thermal pad (bottom surface); dimensions may vary with device reference land pattern layout (reference ipc7351 sop65p640x110-21m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) c
wide input voltage range, high efficiency fault tolerant led driver a8521 35 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com copyright ?2012, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com

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